Program
Here you can download the complete program booklet. And here you find the schedule at a glance.
Monday
14.00 - 18.30 TSS@ETS Free Tutorials
Tutorial A
Mixed-signal/RF design-for-test: principles and advanced techniques
Salvador Mir (TIMA, F)
Tutorial B
Production test practices - How they vary and why?
Jochen Rivoir (Advantest Europe GmbH, D)
19.00 - 21:00 Welcome Reception in Town Hall
Welcome Address by Mayor Heinz Paus
Sponsored by the City of Paderborn
Tuesday
8:45 - 10:00 Opening Session
Opening Ceremony
Welcome Address and Symposium Informaton
Sybille Hellebrand - ETS14 General Chair
Welcome Address
Nikolaus Risch - President of Paderborn U.
Program Introduction
Jerzy Tyszer - ETS14 Program Chair
ETS13 Best Paper Award
Zebo Peng - ETS13 Program Chair
Keynote
Major Eras of Design for Test
Walden C. Rhines, CEO of Mentor Graphics Corp., USA
10:00 - 11:00 Coffee and Posters
Poster Session 1
Chair: Ozgur Sinanoglu (NY University Abu Dhabi, UAE)
A Distance-Based Test Cube Merging Procedure for Compatible and Incompatible Test Cubes
I. Pomeranz
Logic Simulation and Fault Collapsing with Shared Structurally Synthesized BDDs
D. Mironov, R. Ubar, J. Raik
Analysis of Cell-Aware Test Pattern Effectiveness – A Case Study using a 32-bit Automotive Microcontroller
A. Prabhu, V. Vorisek, H. Lang, T. Schumann
A Generic and High-Level Model of Large Unreliable NOCs for Fault Tolerance and Performance Analysis
F. Chaix, Z. Nacer-Eddine, M. Nicolaidis
Property-Checking Based LBIST for Improved Diagnosability
S. Prabhu, V. Acharya, S. Bagri, M. Hsiao
A Collision Resistant Deterministic Random Bit Generator with Fault Attack Detection Possibilities
E. Böhl, M. Lewis, K. Damm
iBoX – Jitter Based Power Supply Noise Sensor
M. Valka, A. Bosio, L. Dilillo, A. Todri, A. Virazel, P. Girard, P. Debaud, S. Guilhot
A Novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR
L. Cassano, G. Di Natale, A. Bosio
11:00 - 12:30 Session 2
Session 2A: Soft errors in processors
Chairs: Zebo Peng (Linköping University, S), Jaan Raik (Tallinn University of Technology, EST)
Two Soft-Error Mitigation Techniques for Functional units of DSP Processors
A. Rohani, H. Kerkhoff
Reducing Embedded Software Radiation-Induced Failures Through Cache Memories
T. Santini, P. Rech, G. Nazar, L. Carro, F. Rech Wagner
Detection Conditions for Errors in Self-adaptive Better-than-worst-case Designs
I. Polian, J. Jiang, A. Singh
Session 2B: ETS2 – Special Track on Emerging Test Solutions
Chairs: Rene Segers (ReSeCo, NL), Matteo Sonza-Reorda (Politecnico di Torino, I), Stefan Eichenberger (NXP, D)
ETS2 is a new initiative to be held for the first time during ETS2014. The ETS2 sessions are characterized by an industrial focus and by flexibility and informality. Consequently, the agenda as listed below is subject to change. During the actual day there may be a switch from one topic to another, and back, depending on the discussions. Also the order of the listed presentations may change, even on the fly.
The main goal is to have a lively discussion on the topics, on the presentations. The ETS2 should act as a podium to discuss both problems as well as potential solutions, in order to motivate all involved, industry and academia, to move forward in the broad area of Test.
Automotive Key Testing Issues
Robert van Rijsinge (NXP)
The Importance of Reliable Data
Andre van de Geijn (Salland Engineering)
The True Value of Test - Testing for Yield Learning
Thomas Hermann (GLOBALFOUNDRIES)
Direct Probe Product Characterization Vehicle Applications
Jimmy Huang et al. (PDF Solutions, USA)
12:30 - 14:00 Lunch
14:00 - 15:30 Session 3
Session 3A: Diagnosis and debug
Chairs: Elham Moghaddam (Mentor Graphics, USA), Stephan Eggersglüß (University of Bremen, D)
Systematic Generation of Diagnostic Software-Based Self-Test Routines for Processor Components
M. Schölzel, T. Koal, H. Vierhaus
Diagnosis of Multiple Faults with Highly Compacted Test Responses
A. Cook, H.-J. Wunderlich
Improving Polynomial Datapath Debugging with HEDs
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, Z. Navabi, M. Fujita
Session 3B: ETS2 – Continued
Chairs: Rene Segers (ReSeCo, NL), Matteo Sonza-Reorda (Politecnico di Torino, I), Stefan Eichenberger (NXP, D)
Telecom (Test) Requirements and Experiences
Xinli Gu (Huawei)
Analog DfT & Test, Lots of Words, no Action
Steve Sunter (Mentor Graphics)
Analog DfT & Test, Experiences and Outlook
Jeff Rearick (AMD)
Optimized DfT Architecture for Analog IP in Automotive Microcontrollers
Helmut Lang (Freescale)
15:30 - 16:00 Coffee and Posters
Poster session 2
Chair: Helmut Lang (Freescale Semiconductor, D)
Towards a General Purpose Mixed-Signal Instrumentation Layer in the Die Stack of a 3D-IC
S. Lin, G. W. Roberts
Automatic Correction of Certain Design Errors Using Mutation Technique
P. Behnam, B. Alizadeh, and Z. Navabi
Power Efficient Scan Testing by Exploiting Existing Error Tolerance Circuitry in a Design
A. Anastasiou, Y. Tsiatouhas
GPU-Based Timing-Aware Test Generation for Small Delay Defects
K.-Y. Liao, P.-J. Chen, A.-F. Lin, J. C.-M. Li, M. Hsiao, L.-T. Wang
Accumulator-based Test-per-clock Scheme for Low-power On-chip Application of Test Patterns
I. Voyiatzis
Quantitative Evaluation of Register Vulnerabilities in RTL Control Paths
L. Chen, M. Ebrahimi, M. Tahoori
Design of Low Cost Fault Tolerant Analog Circuits Using Real-Time Learned Error Compensation
S. Banerjee, A. Gómez-Pau, A. Chatterjee
Homogeneous Many-core Processor System Test Distribution and Execution Mechanism
A. Kamran, Z. Navabi
16:15 - 17:45 Session 4
Session 4A: Security
Mohamed Azimane (NXP, NL), Ioana Elena Vatajelu (Politecnico di Torino, I)
Test-Mode-Only Scan Attack Using the Boundary Scan Chain
O. Sinanoglu, S. Ali, R. Karri
A True Random Number Generator with On-Line Testability
E. Böhl, M. Lewis, S. Galkin
A New Efficiency Criterion for Security Oriented Error Correcting Codes
O. Keren, Y. Neumeier
Session 4B: ETS2 – Continued
Chairs: Rene Segers (ReSeCo, NL), Matteo Sonza-Reorda (Politecnico di Torino, I), Stefan Eichenberger (NXP, D)
Analog DfT & Test : implementing analog Iddq
Pete Sarson (AMS)
Catching Defects that Escape Production Test but Show Up in SLT or as RMA
Harry Chen (Mediatek)
Fighting No Failure Found by Testing Dynamic Faults at Board Level
Artur Jutman (Testonica)
The ins and outs of running a test operational business in Europe
Frederic Mauron (Aptasic)
17:45 - 18:00 Break
18:00 - 19:30 Session 5
Wine and Cheese Panel: Ask the Experts!
Organized by Jeff Rearick (AMD, USA)
19:30 - 21:30 Westphalian Buffet
Wednesday
8:45 - 9:30 Session 6
Keynote
Factoring Variability in the Design/Technology Co-Optimisation (DTCO) in advanced CMOS
Asen Asenov, Department of Electronics and Electrical Engineering, University of Glasgow, UK
9:30 - 10:30 Session 7
Session 7A: Speedpath test and debug
Chairs: Friedrich Hapke (Mentor Graphics, D), Matteo Sonza-Reorda (Politecnico di Torino, I)
Shadow-scan design with low latency overhead and in-situ slack-time monitoring
S. Sarrazin, S. Evain, I. Miro-Panades, A. Valentian, S. Pajaniradja, L. Naviner, V. Gherman
SAT-Based Speedpath Debugging Using Waveforms
M. Dehbashi, G. Fey
Session 7B: Fault injection and mitigation
Chairs: Krish Chakrabarty (Duke University, USA), Ilia Polian (University of Passau, D)
Smart-Hopping: Highly Efficient ISA-Level Fault Injection on Real Hardware
H. Schirmeier, L. Rademacher, O. Spinczyk
Analysis and Mitigation of Single Event Effects on Flash-based FPGAs
L. Sterpone, B. Du
10:30 - 11:00 Coffee Break
11:00 - 12:30 Session 8
Session 8A: Test generation
Chairs: Grzegorz Mrugalski (Mentor Graphics, PL), Bruno Rouzeyre (LIRMM, F)
Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation
M. Wagner, H.-J. Wunderlich
Variation-Aware Deterministic ATPG
M. Sauer I. Polian, M.E. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich, B. Becker
Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
S. Eggersglüß, K. Schmitz, R. Krenz-Baath, R. Drechsler
Session 8B: Analog test in production
Chairs: Florence Azais (LIRMM, F), Alexios Spyronasios (Dialog Semiconductor, D)
Site Dependencies in a Multisite Testing Environment
T. Lehner, A. Kuhr, M. Wahl R. Brück
M-S Specification Binning Based on Digitally Coded Indirect Measurements
A. Gómez-Pau, L. Balado, J. Figueras
Avoiding Burnt Probe Tips: Practical Solutions for Testing Internally Regulated Power Supplies
R. Swanson, A. Wong, S. Ethirajan, A. Majumdar
Session 8C: Vendor Session
Chairs: Said Hamdioui (Delft University of Technology, NL), Giorgio Di Natale (LIRMM, F)
Improving Test Quality while Reducing DFT Costs Through a Hybrid ATPG + Logic BIST Solution
Martin Keim (Mentor Graphics, USA)
New Solutions for Reducing the Time, Effort and Cost of Quality SoC Testing
Rohit Kapur (Synopsys, USA)
ProChek: The Shortcut to Device and Process Qualification, Characterization, Comparison and Reliability Assessment
Hans Manhaeve (Ridgetop Europe nv, B)
12:30 - 14:00 Lunch
14:00 - 15:00 Session 9: Embedded Tutorials
Embedded Tutorial A
Chair: Bernd Becker (University of Freiburg, D)
Error Detection and Recovery in Better-than-Worst-Case Timing Designs
Adit D. Singh (Auburn University, USA)
Embedded Tutorial B
Chair: Görschwin Fey (German Aerospace Center, D)
Fault Injection and Fault Tolerance Methodologies for Assessing Device Robustness and Mitigating against Ionizing Radiation
Dan Alexandrescu (IROC Technologies, F), Luca Sterpone (Politecnico di Torino, I)
Celia Lopez-Ongil (Carlos III University of Madrid, E)
Embedded Tutorial C
Chair: Marie-Lise Flottes (LIRMM, F)
On the Impact of Process Variability and Aging on the Reliability of Emerging Memories
Elena I. Vatajelu, Marco Indaco, Paolo Prinetto (Politecnico di Torino, I)
15:00 - 23:00 Social Event
Thursday
8:45 - 10:15 Session 10
Session 10A: Improving yield and quality
Chairs: Sudhakar Reddy (University of Iowa, USA), Liviu Miclea (Technical University of Cluj-Napoca, RO)
Cell-aware Experiences in a High-Quality Automotive Test Suite
F. Hapke, R. Arnold, M. Beck, M. Baby, S. Straehle, J.F. Goncalves, A. Panait, R. Behr, G. Maugard, A. Prashanthi, J. Schloeffel, W. Redemund, A. Glowatz, A. Fast, J. Rajski
Quantified Contribution of Design for Manufacturing to Yield at 28nm
S. Madhavan, N. Eib, T. Hermann, S. Malik, R. Siegmund
Post-Bond Test of Through-Silicon Vias with Open Defects
R. Rodríguez-Montañés, D. Arumí, J. Figueras
Session 10B: Analog BIST and fault modeling
Chairs: Cedric Mayor (Presto Engineering Europe, F), Wolfgang Vermeiren (Fraunhofer Institute for Integrated Circuits IIS, D)
Optimization of Analog Fault Coverage by Exploiting Defect-Specific Masking
A. Coyette, G. Gielen, W. Dobbelaere, R. van Hooren
INL Systematic Reduced-Test Technique for Pipeline ADCs
E. Peralías, A. Ginés, A. Rueda
Built-In Self-Calibration of CMOS-Compatible Thermopile Sensor with On-Chip Electrical Stimulus
J. Li, Z. Huang, W. Wang
Session 10C: Vendor Session
Chairs: Hans Kerkhoff (Twente University, NL), Xiaoqing Wen (Kyushu Institute of Technology, JP)
TSV BIST™: An Innovative Method for 2.5D / 3D IC Interconnection Integrity Monitoring
Hans Manhaeve (Ridgetop Europe nv, B)
Bit Error Rate Testing (BERT) using FPGA Assisted Test
Jan Heiber (GÖPEL electronic GmbH, D)
ELESIS towards Sophisticated Test Methods
Mohamed Azimane (NXP, NL)
10:15 - 11:00 Coffee and Posters
Poster session 3
Chair: Artur Pogiel (Mentor Graphics, PL)
Triple Error Detection for Imai-Kamiyanagi Codes Based on Subsyndrome Computations
C. Badack, M. Gössel
On-the-Fly Timing-Aware Built-In Self-Repair for High-Speed Interposer Wires in 2.5-D ICs
S.-Y. Huang, Z.-F. ZENG, K.-H. Tsai, W.-T. Cheng
Verification of the Decimal Floating-Point Square Root Operation
A. Sayed Ahmed, H. Fahmy, U. Kuehne
Model Based Generation of High Coverage Test Suites for Embedded Systems
O. Ferrante, A. Ferrari, M. Marazza
Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories
M.-I. Neagu, L. Miclea, S. Manich
Analyzing the Impact of Aging and Voltage Scaling under Neutron-induced Soft Error Rate in SRAM-based FPGAs
F. L. Kastenschmidt, J. Tonfat, T. Both, P. Rech, G. Wirth, R. Reis, F. Bruguier, P. Benoit, L. Torres, C. Frost
Concurrent Online BIST for Sequential Circuits Exploiting Input Reduction and Output Space Compaction
I. Voyiatzis
An Off-line MDSI Interconnect BIST Incorporated in BS 1149.1
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi
11:00 - 12:30 Session 11: Special Sessions
Special Session A -- Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications?
Organized by Luca Sterpone (Politecnico di Torino, I)
An Open Platform for Parameterization and Dynamic Reconfiguration Support in VLIW Processors (Long Presentation)
Stephan Wong and Joost Hoozemans (TU Delft, NL)
Software-based Diagnosis and Reconfiguration in VLIW Processors for Handling Permanent Faults (Short Presentation)
Mario Schölzel (BTU Cottbus, D)
Dependable FPGA-based Reconfiguration for Satellite On-Board Processing (Long Presentation)
Robert Glein, Florian Rittner, Christopher Stender (ISS Fraunhofer, D)
Dynamically Reconfigurable Hardware for Satellite Payload Processing (Short Presentation)
Mario Porrmann (University of Bielefeld, D)
Special Session B
Automotive Electronics
Organized by Piet Engelke (Infineon, D), Chair: Matthias Beck (Infineon Technologies, D), Hans-Joachim Wunderlich (University of Stuttgart, D)
Infineon's Vision on Structural Testing
Stefan Vock (Infineon Technologies, D)
Automotive MEMS Sensors @ Bosch
Matthew Lewis (Robert Bosch AG, D)
12:30 - 14:00 Lunch
14:00 - 15:30 Session 12
Compression and BIST
Chairs: Matthias Beck (Infineon Technologies, D), Paolo Prinetto (Politecnico di Torino, I)
Secure and Efficient LBIST for Feedback Shift Register-Based Cryptographic Systems
E.Dubrova, M. Naslund, G. Selander
On Reducing Test Data Volume by Applying Dynamic Shift under Extremely High Compression Environment
X. Lin, M. Kassab, J. Rajski
Output-Bit Selection with X-Avoidance using Multiple Counters for Test-Response Compaction
W.-C. Lien, K.-J. Lee, K. Chakrabarty, T.-Y. Hsieh
15:30 - 15:45 Closing
